CONFIG DACX

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Action

This statement configures the DACA or DACB in the Xmega.

 

 

Syntax

CONFIG DACx=dac, IO0=IO0,  IO1=IO1, INTERNAL_OUTPUT =INTOTP, CHANNEL=channel, TRIGGER_CH0=trig0,   TRIGGER_CH1=trig1, REFERENCE=ref, LEFT_ADJUSTED=adjusted,  EVENT_CHANNEL=event, INTERVAL=interval,  REFRESH=refresh

 

 

Remarks

DACX	Chose either DACA or DACB. DACA is connected to PORTA. DACB is connected to PORTB.
dac	ENABLED or DISABLED. Chose ENABLED to enable the DAC.
IO0	ENABLED or DISABLED. Chose ENABLED to enable output 0. Each DAC has 2 outputs. When multiple outputs are used, the DAC is using S&H.
IO1	ENABLED or DISABLED. Chose ENABLED to enable output 1.
Intotp	ENABLED or DISABLED. Chose ENABLED to enable the internal output.
Channel	SINGLE or DUAL. If both outputs are used, you need to enable the second output with IO1.
Trig0	ENABLED or DISABLED. Chose ENABLED to enable the trigger of channel 0.
Trig1	ENABLED or DISABLED. Chose ENABLED to enable the trigger of channel 1.
Ref	The DAC needs a stable voltage reference. You can chose one of the following: - INT1V. This will select the internal 1V reference - AVCC. This will use AVCC as reference. - AREFA. This will use AREFA as reference. - AREFB. This will use AREFB as reference. The output of the DAC can never be higher then the voltage reference. When you chose INT1V, the output is from 0-1V in 4096 steps.
Adjusted	ENABLED or DISABLED. By default the DAC output is right adjusted (this means the first 8 Bit are in the Low Byte and the following 4 Bit in the High Byte of the 16-bit Register). You can left alight the result.
Event	The event channel to use for the event system.
Interval	The minimum interval between 2 conversions. This is a value of : 1,2,4,8,16,32,64 or 128. The default in the register is 64. A value of 64 will give an interval of 64 clock cycles.   The value is set in clock cycles and the time in µ Second depend on the CLKper (Peripheral Clock) setting.   The minimum in SINGLE Channel mode is 1µS (1M conversions per seconds). The minimum in DUAL Channel mode (S/H mode) should no be below 1.5µS (666K conversions per second).   In DUAL Channel mode the 50% increase of peripheral clock cycles is AUTOMATICALLY added by the XMEGA chip.
Refresh	The DAC channel refresh timing. This is the interval refresh time in DUAL channel mode. Possible values: OFF 16, 32, 128, 256, 512, 1014, 2048, 4096, 8192, 16384, 32768, 65536. A value of 16 means an interval of 16 clock cycles. The default loaded is 64.   Note: Higher refresh rates causes higher power consumption.   Manual conversions or Events between the refresh intervals do NOT affect the refresh intervals. This means the channels will be refreshed at a constant timing even when the data register are for example updated in between.

 

The DAC data register is available in the DACA0, DACA1 and DACB0 and DACB1 variables.

 

The DAC module can output conversion rates up to 1 M conversions per second with a resolution of 12 bits.

 

A DAC conversion can be triggered by:

•	writing to the DAC data register (DACA0, DACA1 and DACB0 and DACB1)

•	an Event over Event System (when configured to trigger from Event system the DAC data register can be updated several times without triggering an conversion. In case of an Event the latest value in the DAC data register will be used for conversion)

 

Trigger mode can be different between DAC Channels. For example DAC Channel 0 can be setup to work with Events while Channel 1 can be configured to start conversion when DAC data register is updated.

 

How to handle the two Data Channels with one conversion Block:

 
' +-----------+          +------------------+
' | Channel 0 | -------->|                  |-----> Out 0
' +-----------+          | CONVERSION BLOCK |
' +-----------+          |                  |
' | Channel 1 | -------->|                  |-----> Out 1
' +-----------+          +------------------+
'                                 |

'                                            |

'                            Event System

 

The fact that there are two data channels but one conversion block it needs to be configured by CHANNEL.

•	If Channel is SINGLE: Channel 0 is used in continuous-drive output mode and Channel 0 is then always connected to conversion block.

•	If Channel is DUAL: Both channels work in Sample and Hold (S/H) mode. The Sample and Hold keep the DAC output values during a conversion of the other channel. To refresh the output value in DUAL channel mode the refresh timing can be set.

 

 

What can you drive with the XMEGA DAC outputs ?

- The ouputs can drive loads of 1KOhm or capacitive loads of 100pF

 

 

It is possible to use the XMEGA DMA Controller to output data on DAC Channels.

See CONFIG DMACHx, CONFIG DMA

See also Example Nr 2 below.

 

Calibration of DAC

To Calibrate to DAC you can use the values from the signature row or you can change manual the Dacb_ch0offsetcal andDacb_gaincal register.

For example for using signature row for DACB Ch0 this is:

 

'DACB
B = Readsig(32)                                             'DACB Calibration Byte 0 (DACBOFFCAL)
Dacb_ch0offsetcal = B                                       'write to the DACB offset register
Print #1 , "DACB Calibration Byte 0 = " ; B
B = Readsig(33)                                             'DACB Calibration Byte 1 (DACBGAINCAL)
Dacb_gaincal = B
Print #1 , "DACB Calibration Byte 1 = " ; B

 

See also Atmel Application Note AVR1301 for further details.

 

See also

START , STOP , CONFIG EVENT_SYSTEM

 

 

Example Nr 1

(For another example see also the example xm128a1.bas from the samples\chips folder)

Example Nr 2 (Ouput an Array of data from SRAM to DAC B over DMA)

(This example is generating an sawtooth wave on DAC B Channel 0 = Portb.2 on ATXMEGA256A3B)