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| − | + | = <span class="f_Header">Funktion</span> = | |
| − | + | Freigeben des angegebenen Interrupts. | |
<span style="font-family: Arial;"> </span> | <span style="font-family: Arial;"> </span> | ||
Revision as of 23:40, 11 March 2013
Contents |
Funktion
Freigeben des angegebenen Interrupts.
Syntax
ENABLE interrupt [, prio]
Remarks
|
Interrupt |
Description |
|
INT0 |
External Interrupt 0 |
|
INT1 |
External Interrupt 1 |
|
OVF0,TIMER0, COUNTER0 |
TIMER0 overflow interrupt |
|
OVF1,TIMER1,
COUNTER1 |
TIMER1 overflow interrupt |
|
CAPTURE1, ICP1 |
INPUT CAPTURE TIMER1 interrupt |
|
COMPARE1A,OC1A or
COMPARE1, OC1 |
TIMER1 OUTPUT COMPARE A interrupt
In case of only one compare interrupt |
|
COMPARE1B,OC1B |
TIMER1 OUTPUT COMPARE B interrupt |
|
SPI |
SPI interrupt |
|
URXC |
Serial RX complete interrupt |
|
UDRE |
Serial data register empty interrupt |
|
UTXC |
Serial TX complete interrupt |
|
SERIAL |
Disables URXC, UDRE and UTXC |
|
ACI |
Analog comparator interrupt |
|
ADC |
A/D converter interrupt |
| |
|
|
XMEGA ONLY |
|
|
prio |
The priority you want to assign to the interrupt. Specify Lo, Hi or Med. In the Xmega you must provide the priority of the interrupts. Lo=Low priority. Hi=High priority and Med=Medium priority. If you do not specify a priority, MED will be used. |
By default all interrupts are disabled.
The global interrupts master switch is also disabled by default.
If you enable an interrupt, it will only fire if the master interrupt switch is enabled.
You enable this master switch with ENABLE INTERRUPTS.
You can disable it with DISABLE INTERRUPTS.
If an interrupt is executed, the global master switch will be disabled automatically by the hardware.
This is to prevent other interrupts to occur.
When the interrupt routine returns, the processor hardware will automatically enable the master switch so new interrupts may occur.
It depends on the processor how many and which interrupts it has. If you type ENABLE in the editor, you will get a pop up with a list of interrupts you can chose from.
XMEGA
In normal AVR chips the priority is determined by the interrupts address. The lower the address, the higher the priority.
In the DAT file you can find a list with interrupts and their address.
For example , taken from the m1280def.dat file "
[INTLIST]
count=56
INTname1=INT0,$002,EIMSK.INT0,EIFR.INTF0
INTname2=INT1,$004,EIMSK.INT1,EIFR.INTF1
INTname3=INT2,$006,EIMSK.INT2,EIFR.INTF2
INTname4=INT3,$008,EIMSK.INT3,EIFR.INTF3
INTname5=INT4,$00a,EIMSK.INT4,EIFR.INTF4
INTname6=INT5,$00c,EIMSK.INT5,EIFR.INTF5
INT0 has the highest priority since it has the lowest address (address 2)
The XMEGA has a priority system. You can specify if an interrupt as a low, medium or high priority.
But you MUST enable these priorities with CONFIG PRIORITY
If you use LO and MED priority, they have to be enabled.
See also
DISABLE , ON , CONFIG PRIORITY
Partial Example
Enable Interrupts 'allow interrupts to be set Enable Timer1 'enables the TIMER1 interrupt
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